Protection of software algorithms executed on secure modules

Loop structures in software code may reveal essential information about implemented algorithms and their parameters, even if the observer has no knowledge about which instructions are executed. Regular patterns can for instance be observed in power consumption, instruction fetches in external memory, or radiated EM energy. This paper addresses the use of dummy operations to obscure the details of the algorithm executed by the processor. We show that for a particular class of dummy insertion strategies, a Viterbi decoder can fairly reliably distinguish dummy fetches from real instruction fetches. In the second part of this paper, we study strategies to choose dummy fetches from a more general model. For certain situations, the optimum protection strategy appears to be deterministic (as opposed to random). Moreover, we show that in such a case, it is fundamentally not possible to enhance the security of the implementation by keeping the strategy for generating dummy fetches secret to the attacker. Author Keywords: Software protection; Secure processor; Viterbi decoder; Dummy instruction

Nonblocking self-routing switching networks

We investigate a class of binary self-routing switches, characterized by the way they function. These switches can describe for example the functional aspects of some recently developed self-routing photonic switches. First we show that, within this class, essentially we only need to consider the four possible types of fixed-directory routing switches. Then we determine exactly the minimum number of switches contained in an M-input N-output wide-sense nonblocking self-routing network composed of switches from this class

Optimal interconnect ATPG under a ground-bounce constraint

In order to prevent ground bounce, Automatic Test Pattern Generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximal Hamming distance between any two consecutive test patterns to a user-defined integer, referred to as the Simultaneously-Switching Outputs Limit (SSOL). The conventional approach to meet this SSOL constraint is to insert additional test patterns between consecutive test patterns if their Hamming distance is too large; this approach often leads to substantially more test patterns than strictly necessary. This paper presents an algorithm that generates, for a user-defined number of interconnect wires, a minimal set of test patterns that respects a user-defined SSOL constraint. Experimental results show that, in comparison to the conventional approach, our algorithm leads to a significant reduction of up to 60% in the test pattern count and corresponding test application time

On codes with covering radius 1 and minimum distance 2

AbstractWe show that a code C of length n over an alphabet Q of size q with minimum distance 2 and covering radius 1 satisfies |C| ≥ qn−1/(n − 1). For the special case n = q = 4 the smallest known example has |C| = 31. We give a construction for such a code C with |C| = 28

Protection of software algorithms executed on secure modules

Loop structures in software code may reveal essential information about implemented algorithms and their parameters, even if the observer has no knowledge about which instructions are executed. Regular patterns can for instance be observed in power consumption, instruction fetches in external memory, or radiated EM energy. This paper addresses the use of dummy operations to obscure the details of the algorithm executed by the processor. We show that for a particular class of dummy insertion strategies, a Viterbi decoder can fairly reliably distinguish dummy fetches from real instruction fetches. In the second part of this paper, we study strategies to choose dummy fetches from a more general model. For certain situations, the optimum protection strategy appears to be deterministic (as opposed to random). Moreover, we show that in such a case, it is fundamentally not possible to enhance the security of the implementation by keeping the strategy for generating dummy fetches secret to the attacker. Author Keywords: Software protection; Secure processor; Viterbi decoder; Dummy instruction